A Low-Impedance, Sub-Bandgap 0.6μm CMOS Reference with 0.84% Trimless 3-σ Accuracy and –30dB Worst-Case PSRR up to 50MHz
نویسندگان
چکیده
Modern mobile applications demand high performance from low supply voltages to reduce power (extend battery life) and survive low breakdown voltages (imposed by sub-micron CMOS technologies), which is why precise low-impedance subbandgap references (below 1.2V) that are independent of process, package stress, supply, load, and temperature are critical. However, improving dc accuracy by trimming requires test time (cost) in production and dynamic-element matching (DEM) introduces switching noise. Additionally, improving ac accuracy by rejecting supply ripple with cascodes increases headroom requirements and shunting coupled noise with series lowimpedance buffers introduces temperature-sensitive offsets that degrade dc accuracy. This paper presents a prototyped 0-5mA, 890mV, low-impedance, 0.6μm CMOS reference with a trimless 3-σ unloaded dc accuracy of 0.84% across -40C and 125C (2.74% when loaded with 0-5mA and supplied from 1.8-3V) and a worst-case powersupply ripple rejection (PSRR) of -30dB up to 50MHz. The design adopts a low-cost, noise-free, self-selecting Survivor scheme to automatically select the best matching pair of devices among a bank of similar pairs during start-up (or power-on reset) and use them
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تاریخ انتشار 2014